Video Pipeline Architect- Platform Architecture
Santa Clara Valley (Cupertino), California, United States
Hardware
Summary
Posted: Nov 7, 2018
Role Number: 200008851
Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture visionary who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to design how all of our technologies work in unison. In this role, you will be interfacing with software and hardware architects, designers and validation engineers to develop efficient SOC architectures for complex pixel processing and memory compression systems.
Key Qualifications
- The ideal candidate will have 5+ years experience in video codec architecture design working on hardware architectures for complex video processors:
- Experience working on all aspects of video codec processing including motion estimation, transform/quantization, motion compensation, entropy coding
- Expert knowledge of video coding standards including MPEG-4, H.264, HEVC
- Expert knowledge of digital signal processing and information theory and its applications to video compression
- Experience developing C/C++ bit accurate models for hardware validation
- Knowledge of scripting languages such as Perl and/or Python
- Experience developing hardware video codecs from concept to products
- Experience evaluating compression efficiency performance of video encoders
Description
As a Platform Architect owning the architecture for various pixel processing algorithms, you will have responsibilities spanning various aspects of video pipeline architecture: Develop power and area efficient hardware architectures for various video processing IP. Write clear and concise hardware architecture specifications. Develop bit-accurate C-models for hardware/software verification. Work with design and verification teams to define and implement pixel IP data and control path architectures. Work with memory system architects to define define and implement pixel IP DMA architectures. Work across teams to make correct trade-offs between quality, complexity and schedule.The ideal candidate will have 5+ years experience in video pipeline architectures with the following background: Experience writing hardware architecture specifications. Experience working on various pixel processing IP such as scaling, tone mapping and enhancement. Experience developing C/C++ bit accurate models for hardware design verification. Knowledge of compression algorithms. Knowledge of memory interface and transaction architectures. Knowledge of signal processing theory and how it applies to image/video processing algorithms. Knowledge in hardware micro-architecture. Knowledge of scripting languages such as Perl and/or Python Strong communication skills and ability to work across various groups.
Education & Experience
BS/MS in EE/CS
Additional Requirements
See job description